- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67689 > ICS8430AYI-71LFT (INTEGRATED DEVICE TECHNOLOGY INC) 700 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF資料下載
參數(shù)資料
| 型號： | ICS8430AYI-71LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-32 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 211K |
| 代理商： | ICS8430AYI-71LFT |
8430AYI-71
www.icst.com/products/hiperclocks.html
REV. B JANUARY 27, 2005
8
Integrated
Circuit
Systems, Inc.
ICS8430I-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2B. LVPECL OUTPUT TERMINATION
FIGURE 2A. LVPECL OUTPUT TERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
APPLICATION INFORMATION
Figure 3. CRYSTAL INPUt INTERFACE
C2
22p
C1
18p
X1
18pF Parallel Crystal
XTAL2
XTAL1
CRYSTAL INPUT INTERFACE
The ICS8430I-71 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in
Figure 3 below were determined using a 25MHz, 18pF par-
allel resonant crystal and were chosen to minimize the ppm
error. These same capacitor values will tune any 18pF paral-
lel resonant crystal over the frequency range and other pa-
rameters specified in this data sheet. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS8430BY-71LF | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430BYI-71 | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430BYI-71T | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DY-01T | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DY-111LF | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8430BI-71L | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY-71 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY71L | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY-71LF | 功能描述:IC SYNTHESIZR DUAL LVPECL 32LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8430BY-71LFT | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。