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| 型號(hào)： | ICS870919BRI-01LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GENERATOR LVCMOS 28QSOP |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | HiPerClockS™ |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 管件 |
| 其它名稱： | 800-2397-5 ICS870919BRI-01LF-ND |
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ICS870919BVI-01 REVISION C JANUARY 6, 2012
11
2012 Integrated Device Technology, Inc.
ICS870919I-01 Data Sheet
LVCMOS CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS870919I-01.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS870919I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *5mA = 18mW
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 11)] = 29.5mA
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)
2 = 11
* (29.5mA)2 = 9.57mW per output
Total Power (ROUT) = ROUT (per output) * number of outputs = 9.57mW * 8 outputs = 76.56mW
Dynamic Power Dissipation for Q = 80MHz
Power (80MHz) = CPD * Frequency * (VDD)
2 = 330pF * 80MHz * (3.6V)2 = 342mW
Total Power
= Power (core)MAX + Total Power (ROUT) + Power (80MHz)
= 18mW + 76.56mW + 342mW
= 436.56mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 66°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.437W * 66°C/W = 113.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for a 28 Lead QSOP, Forced Convection
JA by Velocity
Linear Feet per Minute
0200
500
Multi-Layer PCB, JEDEC Standard Test Boards
66.0°C/W
58.3°C/W
55.2°C/W
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