參數(shù)資料
型號: ICS874005AG-04LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/13頁
文件大小: 0K
描述: IC PCI EXPRSS/JITT ATTEN 24TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: HiPerClockS™, FemtoClock™, PCI Express® (PCIe)
類型: 扇出緩沖器(分配),漂移衰減器
PLL:
主要目的: PCI Express(PCIe)
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 320MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: 800-2400-5
874005AG-04LF
ICS874005AG-04LF-ND
PCI EXPRESS JITTER ATTENUATOR
ICS874005-04
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
1
ICS874005AG-04 REV. A JULY 29, 2008
GENERAL DESCRIPTION
The ICS874005-04 is a high performance Diff-
erential-to-LVDS Jitter Attenuator designed for use
in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. T h e
ICS874005-04 has 2 PLL bandwidth modes: 300kHz and
2MHz. The 300kHz mode will provide maximum jitter
attenuation, but higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles. The ICS874005-04
supports Serdes reference clock frequencies of 100MHz,
125MHz and 250MHz.
The ICS874005-04 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
FEATURES
Five differential LVDS output pairs
One differential clock input
Supports 100MHz, 125MHz, and 250MHz Serdes reference
clocks
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 320MHz
Input frequency range: 98MHz - 128MHz
PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
RMS phase jitter @ 100MHz (1.875MHz – 20MHz):
0.88ps (typical)
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
3.3V operating supply
Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
HiPerClockS
ICS
QA0
nQA0
BLOCK DIAGRAM
BW_SEL
0 = PLL Bandwidth: ~300kHz (default)
1 = PLL Bandwidth: ~2MHz
PLL BANDWIDTH
F_SELA
0
÷5 (default)
1
÷4
F_SELB
0
÷2 (default)
1
÷4
VCO
490 - 640MHz
Phase
Detector
M = ÷5 (fixed)
Pulldown
OEA
F_SELA
BW_SEL
CLK
nCLK
F_SELB
MR
OEB Pullup
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pulldown
Pullup
Pulldown
PIN ASSIGNMENT
ICS874005-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
nQB2
nQA1
QA1
VDDO
QA0
nQA0
MR
BW_SEL
VDDA
F_SELA
VDD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
QB2
VDDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
nCLK
CLK
24
23
22
21
20
19
18
17
16
15
14
13
Pulldown
QB2
nQB2
0 = ~300kHz
1 = ~2MHz
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