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參數(shù)資料
| 型號(hào)： | ICS9341 |
| 英文描述： | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| 中文描述： | 133MHz的時(shí)鐘發(fā)生器和集成緩沖器，用于PowerPC的⑩ |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 207K |
| 代理商： | ICS9341 |
ICS9341
Pin Descriptions
Pin number
1
2
3
4, 16
5, 6, 7, 8, 17, 18,
19, 20
9, 24
10
11, 12, 13, 14
15
21, 22
Pin name
Type
PWR
IN
OUT
PWR
Description
GNDREF
X1
X2
VDDPCI
Ground pin for REF clocks.
XTAL_IN 14.318MHz crystal input.
XTAL_OUT Crystal output.
3.3Volts power pin for PCICLKs.
PCICLK (1:8)
OUT
PCI clock output at 3.3V. Synchronous to CPU clocks.
GNDPCI
GNDCPUB
CPUB (1:4)
VDDCPUB
FS (0:1)
PWR
PWR
OUT
PWR
IN
Ground pin for PCI clocks.
Ground pin for CPUB clocks.
CPUCLK outputs up to 133.3MHz.
Power pin for the CPU bank B CLKs. 3.3V.
Logic - input for frequency selection.
These control the output functionality of the OUT and OUT/2 pins.
Refer to table for details.
Gnd pin for PCICLKs.
Power for analog outputs.
This active low input stops PCI clocks.
Not connected
Digitial ground
Analog ground
Ground for output pins.
Half the OUT frequency. Dependent on OUT_SEL. Refer to table
for details.
This output frequency is dependent on OUT_SEL. Refer to table for
details.
Power for OUT pins 3.3V.
Power for digitial outputs.
This active low input stops the CPUB clocks at a logic "0" level
when input low.
CPUCLK outputs up to 133.3MHz.
Power pin for the CPU bank A CLKs. 3.3V.
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
Ground pin for CPUB clocks.
Spread spectrum is turned on by driving this input high and turned
off by driving low.
Power pin for REF clocks.
14.318MHz reference clock outputs at 3.3V.
23, 41
*OUT_SEL (0:1)
IN
24
25
26
GNDPCI
VDDA
*PCI_STOP#
N/C
GNDD
GNDA
GNDOUT
PWR
PWR
IN
-
PWR
PWR
PWR
27, 28
29
30
31
32
OUT/2
OUT
33
OUT
OUT
34
35
VDDOUT
VDDD
PWR
PWR
36
CPUB_STOP#**
IN
45, 44, 38, 37
39
CPUA (1:4)
VDDCPUA
OUT
PWR
40
PD#
IN
42
GNDCPUA
PWR
43
SS_EN
IN
46
VDDREF
REF
PWR
OUT
47, 48
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9341yF | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342yF-T | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342 | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | DDR Phase Lock Loop Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9341YF | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342 | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342AFLF | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9342YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
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