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參數(shù)資料
| 型號： | ICS93720YGLFT |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 291K |
| 代理商： | ICS93720YGLFT |
7
ICS93720
Preliminary Product Preview
Recommended Layout for the ICS93720
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1)
Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2)
Make all power and ground traces are as wide as the via
pad for lower inductance.
3)
VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4)
Notice that ground vias are never shared.
5)
When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6)
Differential mode clock output traces are routed:
a.
With a ground trace between the pairs. Trace is
grounded on both ends.
b.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
Component Values:
Ref Desg.
Value
Description
Package
C1,C4,C5,
C7,C11,C12
.01uF
CERAMIC MLC
0603
C2,C3,C8,
C9
4.7uF
CERAMIC MLC
1206
C10
.22uF
CERAMIC MLC
0603
C6
2200pF
CERAMIC MLC
0603
R12
120
0603
R9
4.7
0603
U1
ICS93701AG
TSSOP48
C2
4.7uF
1
2
V2P5
FB_IN#
C3
4.7uF
1
2
V2A5
C9
4.7uF
1
2
C7
.01uF
1
2
V2P5
C16
.01uF
1
2
C10
.22uF
1
2
C1
.01uF
1
2
C5
.01uF
1
2
C11
.01uF
1
2
R12
120
1
2
V2A5
CLK_IN#
U1
ICS93701
16
4
11
15
21
28
34
38
45
1
7
8
18
24
25
31
41
42
48
17
35
36
13
14
37
12
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
33
32
AVDD
VDD
GND
AGND
FB_INT
FB_INC
CLK_INT
CLK_INC
SDA
SCL
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
C12
.01uF
1
2
C6
.0022pF
1
2
SCL
R9
4.7
1
2
C13
.01uF
1
2
SDA
C14
.01uF
1
2
FB_IN
C8
4.7uF
1
2
C15
.01uF
1
2
CLK_IN
C4
.01uF
1
2
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| ICS93722 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Cost DDR Phase Lock Loop Zero Delay Buffer |
| ICS93722CFLF | 功能描述:IC DDR PLL ZD BUFFER 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS93722CFLFT | 功能描述:IC DDR PLL ZD BUFFER 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS93722YFLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Low Cost DDR Phase Lock Loop Zero Delay Buffer |
| ICS93725 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR and SDRAM Zero Delay Buffer |
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