- 您現在的位置：買賣IC網 > PDF目錄1999 > ICS94201DFLF (IDT, Integrated Device Technology Inc)IC FREQ GENERATOR PROGR 56-SSOP PDF資料下載
參數資料
| 型號： | ICS94201DFLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 19/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FREQ GENERATOR PROGR 56-SSOP |
| 標準包裝： | 26 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:29 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 500.03MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 56-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 94201DFLF |
9
ICS94201
0428B - 11/28/05
Byte 16: Spread Sectrum Control Register
Byte 17: Spread Spectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 18: Output Dividers Control Register
Byte 19: Output Dividers Control Register
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass.
t
i
BD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
BX
7
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
6
t
i
BX
6
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
5
t
i
BX
5
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
4
t
i
BX
4
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
3
t
i
BX
3
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
2
t
i
BX
2
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
1
t
i
BX
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
0
t
i
BX
0
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
t
i
BD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
BX
5
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
6
t
i
BX
4
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
5
t
i
BX
3
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
4
t
i
BX
2
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
3
t
i
BX
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
2
t
i
BX
0
1
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
1
t
i
BX
9
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
0
t
i
BX
8
t
i
B
l
o
r
t
n
o
C
X
U
M
r
e
d
i
v
i
D
t
u
p
t
u
O
t
i
BD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
BX
7
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
6
t
i
BX
6
t
i
B
m
u
r
c
e
p
S
d
a
e
r
p
S
5
t
i
BX
5
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
4
t
i
BX
4
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
BX
3
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
BX
2
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
BX
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
BX
0
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
t
i
BD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
BX
6
2
t
i
B
l
o
r
t
n
o
c
r
e
d
i
v
i
D
6
t
i
B0
5
2
t
i
B
l
o
r
t
n
o
c
r
e
d
i
v
i
D
5
t
i
BX
4
2
t
i
B
l
o
r
t
n
o
c
r
e
d
i
v
i
D
4
t
i
BX
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
BX
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
BX
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
BX
9
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
BX
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with the wrong spread percentage and/or group to group divider ratio
programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. Users can also utilize software utility provided to program the VCO frequency from ICS Application Engineering.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spread amount desired.
See Application note for software support.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS950218AF | IC TIMING CTRL HUB P4 48-SSOP |
| ICS950908BFLF | IC TIMING CTRL HUB P4 56-SSOP |
| ICS951402AGLF | IC TIMING CTRL HUB P4 48-TSSOP |
| ICS95V847AGIT | IC CLOCK DRIVER 2.5V 24-TSSOP |
| ICS95V850AGT | IC CLK DVR PLL 1:10 48TSSOP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS94201DFLFT | 功能描述:IC FREQ GENERATOR PROGR 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS94201DFT | 功能描述:IC FREQ GENERATOR PROGR 56-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS94201YFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable System Frequency Generator for PII/III⑩ |
| ICS94203 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable System Frequency Generator for PII/III⑩ |
| ICS94203F-T | 制造商:ICS 制造商全稱:ICS 功能描述:Peripheral IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。