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參數(shù)資料
| 型號： | ICS94203 |
| 英文描述： | 18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 可編程系統(tǒng)頻率發(fā)生器有價證券/三⑩ |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 183K |
| 代理商： | ICS94203 |
10
ICS94203
Byte 21: ICS Reserved Register
Notes:
1. PWD = Power on Default
Byte 22: Output Rise/Fall Time Select Register
Byte 20: Output Dividers Control Register
Note: Changing bits in these registers results in
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware
(latch inputs FS[0:4]) or I
2
C (Byte 0 bit [1:7]) setting. Be sure
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is
intended, Byte 21-22 will lose their default power up value.
Note: Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all of the above clocks.
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