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參數資料
| 型號： | ICS94203 |
| 英文描述： | 18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 可編程系統(tǒng)頻率發(fā)生器有價證券/三⑩ |
| 文件頁數： | 4/18頁 |
| 文件大?。?/td> | 183K |
| 代理商： | ICS94203 |
4
ICS94203
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Readback will support standard SMBUS controller protocol.
The number of bytes to readback is defined by writing to
byte 6.
When writing to byte 14 - 15, byte 16 - 17 and byte 18 - 20, they must be written as a set.
If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
2.
3.
4.
5.
6.
7.
Notes:
Register Name
Byte
Description
Output frequency, hardware / I
2
C frequency
select, spread spectrum & output enable
control register.
Pwd Default
Functionality & Frequency Select
Register
0
See individual byte
description
Output Control Registers
1-5
Active / inactive output control registers.
See individual byte
description
Byte Count Read Back Register
6
Writing to this register will configure byte
count and how many byte will be read back.
Do not write 00
H
to this byte.
The inverse of the latched inputs level could
be read back from this register.
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
This bit select whether the output frequency
is control by hardware/byte 0 configurations
or byte 14&15 programming.
Writing to this register will configure the
number of seconds for the watchdog timer
to reset.
This is an unused register. Writing to this
register will not affect device functionality.
Byte 11 bit[3:0] is ICS vendor id - 0001.
Other bits in these 2 registers designate
device revision ID of this part.
Don't write into this register, writing 1's will
cause malfunction.
These registers control the dividers ratio
into the phase detector and thus control the
VCO output frequency.
06
H
Latched Inputs Read Back
Register
7
See individual byte
description
Watchdog Control Registers
8 Bit[6:0]
000,0000
VCO Control Selection Bit
8 Bit[7]
0
Watchdog Timer Count Register
9
FF
H
ICS Reserved Register
10
00
H
Device ID, Vendor ID & Revision ID
Registers
11-12
See individual byte
description
ICS Reserved Register
13
00
H
VCO Frequency Control Registers
14-15
Depended on
hardware/byte 0
configuration
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
16-17
These registers control the spread
percentage amount.
Output Dividers Control Registers
18-20
Changing bits in these registers result in
frequency divider ratio changes. Incorrect
configuration of group output divider ratio
can cause system malfunction.
Increment or decrement the group skew
amount as compared to the initial skew.
These register will control the group rise
and fall time.
Depended on
hardware/byte 0
configuration
Group Skews Control Registers
21
See individual byte
description
See individual byte
description
Output Rise/Fall Time Select
Registers
22
Brief I
2
C registers description for ICS94203
Programmable System Frequency Generator
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