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參數(shù)資料
| 型號(hào)： | ICS950813 |
| 英文描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 中文描述： | 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分 |
| 文件頁(yè)數(shù)： | 11/22頁(yè) |
| 文件大小： | 265K |
| 代理商： | ICS950813 |
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11
ICS950813
Advance Information
0708—10/10/02
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+ 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
Input Low Current
CONDITIONS
MIN
2
TYP
MAX
UNITS
V
V
mA
mA
V
DD
+ 0.3
0.8
5
V
SS
- 0.3
-5
-5
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
Operating Supply
Current
I
DD3.3OP
C
L
= Full load; Select @ 100 MHz
229
280
mA
I
DD3.3OP
C
L
=Full load; Select @ 133 MHz
IREF=5 mA
V
DD
= 3.3 V
220
280
45
mA
Powerdown Current
Input Frequency
Pin Inductance
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
mA
MHz
nH
pF
pF
pF
7
5
6
Logic Inputs
Output pin capacitance
X1 & X2 pins
From Assertion of PWRSAVE# to 1st
clock.
From PowerUp or deassertion of
PowerDown to 1st clock.
Output enable delay (all outputs)
Output disable delay (all outputs)
27
30
33
PWRSAVE
Stabilization
1,2
T
PWRSV
1.8
ms
Clk Stabilization
1,2
T
STAB
1.8
ms
t
PZH
,t
PZL
t
PHZ
,t
PLZ
1
1
10
10
ns
ns
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for buffered and un-buffered timing requirements.
Delay
1
Input Capacitance
1
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