參數(shù)資料
型號(hào)： ICS950818
英文描述： Frequency Generator with 200MHz Differential CPU Clocks
中文描述： 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 165K
代理商： ICS950818
Integrated
Circuit
Systems, Inc.
ICS950818
0825F—11/19/03
Block Diagram
Recommended Application:
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
processor.
Output Features:
2 - Differential CPU Clock Pairs @ 3.3V
8 - PCI (3.3V) @ 33.3MHz including 2 1x/2x
selectable PCI clocks
3 - PCI_F/PCI selectable (3.3V) @ 33.3MHz
1 - USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 - REF (3.3V) @ 14.318MHz
4 - 3V66 (3.3V) @ 66.6MHz
1 - VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Selectable 1X or 2X strength for REF and PCI via
SMBus interface
Programmable group to group skew
Linear programmable frequency and spreading %
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through
SMBus interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Pin Configuration
Frequency Generator with 200MHz Differential CPU Clocks
X1 1
X2 2
GND 3
48 VDDREF
47 REF
46 FS1
45 CPU_STOP#
44 VDDCPU
43 CPUCLKT0
42 CPUCLKC0
41 GND
40 VDDCPU
39 CPUCLKT1
38 CPUCLKC1
37 IREF
36 FS0
35 48MHz_USB
34 48MHz_DOT
33 VDD48
32 GND
31 3V66_1/VCH_CLK
30 PCI_STOP#
29 PCICLK10
28 VDD3V66
27 GND
26 SCLK
25 SDATA
PCICLK_F0/PCICLK6 4
PCICLK_F1/PCICLK7 5
PCICLK_F2/PCICLK8 6
GND 7
PCICLK0 8
PCICLK1 9
*PCICLK2 10
VDDPCI 11
*PCICLK3 12
PCICLK4 13
PCICLK5 14
VDD3V66 15
GND 16
3V66_2 17
3V66_3 18
3V66_4 19
PCICLK9 20
PD# 21
VDDA 22
GND 23
Vtt_PWRGD# 24
I
48-Pin 6.10 mm. Body, 0.50 mm. pitch TSSOP
*These outputs have selectable 1X/2X strength via SMBus
Frequency Select Table 1
Freq
Sel
FS
1
0
0
1
1
FS
0
0
1
0
1
100.00
166.67
133.33
200.00
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
14.318
14.318
14.318
14.318
48.008
48.008
48.008
48.008
3V66(4:1)
MHz
CPU MHz
USB/DOT
MHz
REF MHz
PCI MHz
PLL2
PLL1
Spread
Spectrum
3V66 (4:2)
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66
DIVDER
PD#
Vtt_PWRGD#
CPU_STOP#
PCI_STOP#
FS (1:0)
SDATA
SCLK
I REF
Control
Logic
Config.
Reg.
REF
CPUCLKT (1:0)
CPUCLKC (1:0)
CPU
DIVDER
3
3
Stop
3V66_1/VCH_CLK
PCICLK (10:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
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