2C Table: Reserved Register
參數(shù)資料
型號: ICS951402AGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 21/23頁
文件大?。?/td> 0K
描述: IC TIMING CTRL HUB P4 48-TSSOP
標準包裝: 1,000
系列: TCH™
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU,Timing Control Hub?
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無/是
頻率 - 最大: 210MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
其它名稱: 951402AGLFT
7
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2C Table: Reserved Register
Byte 3
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
Reserved
RW
-
1
Bit 6
-
Reserved
RW
-
1
Bit 5
-
Reserved
RW
-
1
Bit 4
-
Reserved
RW
-
1
Bit 3
-
Reserved
RW
-
1
Bit 2
-
Reserved
RW
-
1
Bit 1
-
Reserved
RW
-
1
Bit 0
-
Reserved
RW
-
1
I
2C Table: Functionality and Frequency Select Register
Byte 4
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
FS3
Freq Select Bit 7
RW
0
Bit 6
-
FS2
Freq Select Bit 6
RW
0
Bit 5
-
FS1
Freq Select Bit 5
RW
0
Bit 4
-
FS0
Freq Select Bit 4
RW
See
Frequency Table
0
Bit 3
-
FS Source
Frequency H/W or
IIC Select
RW
Latch Input
IIC
0
Bit 2
-
FS4
Freq Select Bit 2
RW
See Frequency Table
0
Bit 1
-
SS_EN
SPREAD Enable
RW
OFF
ON
1
Bit 0
-
All Outputs
Output Control
RW
Normal
Tri-state
0
Note: If Byte4 bit1 = 0 then FS4=0
I
2C Table: Output Control and Read Back Register
Byte 5
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
31
AGP1
Output Control
RW
Disable
Enable
1
Bit 6
32
AGP0
Output Control
RW
Disable
Enable
1
Bit 5
26
24_48#SEL
24 or 48 Select
RW
48MHz
24MHz
X
Bit 4
-
FS4RB
FS4 Read back
R
-
X
Bit 3
-
FS3RB
FS3 Read back
R
-
X
Bit 2
-
FS2RB
FS2 Read back
R
-
X
Bit 1
-
FS1RB
FS1 Read back
R
-
X
Bit 0
-
FS0RB
FS0 Read back
R
-
X
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