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參數(shù)資料
| 型號： | ICS952623 |
| 英文描述： | Programmable Timing Control Hub for Next Gen P4 processor |
| 中文描述： | 可編程定時控制中心，為下一代P4處理器 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 329K |
| 代理商： | ICS952623 |
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21
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU Clock Tristate Timing
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
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| ICS952623YFT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623YGT | Programmable Timing Control Hub for Next Gen P4 processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS952623YFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623YGT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952702 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952702YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952703 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for K7 System |
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