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參數(shù)資料
| 型號： | ICS9DB108 |
| 英文描述： | Eight Output Differential Buffer for PCI-Express |
| 中文描述： | 8個輸出差分緩沖器支持PCI - Express |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 109K |
| 代理商： | ICS9DB108 |
11
Integrated
Circuit
Systems, Inc.
ICS9DB108
0723D—01/08/04
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD#, Power Down
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x I
REF
and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PD# Assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.
PD# De-assertion
PWRDWN#
DIF
DIF#
PWRDWN#
DIF
DIF#
Tstable
<1mS
Tdrive_PwrDwn#
<300uS, >200mV
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9DB108BF | 制造商:ICS 功能描述: |
| ICS9DB108BFLF | 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS9DB108BFLFT | 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| ICS9DB108BG | 制造商:INT_CIR_SYS 功能描述: |
| ICS9DB108BGLF | 功能描述:IC BUFFER 8OUTPUT DIFF 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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