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參數(shù)資料
| 型號： | ICS9LPR501 |
| 英文描述： | 64-pin CK505 w/Fully Integrated Voltage Regulator |
| 中文描述： | 64引腳CK505瓦特/全集成穩(wěn)壓器 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 250K |
| 代理商： | ICS9LPR501 |
3
Integrated
Circuit
Systems, Inc.
ICS9LPR501
1118E—08/08/07
Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
17
SRCT1/SE1
OUT
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100
MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup
default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus
B1b[4:1]
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
18
SRCC1/SE2
OUT
19
20
21
22
23
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
PWR
PWR
OUT
OUT
PWR
24
SRCT3/CR#_C
I/O
25
SRCC3/CR#_D
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1
or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of
SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte
6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
26
27
28
29
30
31
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
PWR
I/O
I/O
PWR
OUT
OUT
32
SRCC11/CR#_G
I/O
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