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參數(shù)資料
| 型號(hào)： | ICS9LPR501 |
| 英文描述： | 64-pin CK505 w/Fully Integrated Voltage Regulator |
| 中文描述： | 64引腳CK505瓦特/全集成穩(wěn)壓器 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 250K |
| 代理商： | ICS9LPR501 |
4
Integrated
Circuit
Systems, Inc.
ICS9LPR501
1118E—08/08/07
Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
33
SRCT11/CR#_H
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of
SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3 bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using
byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
True clock of differential SRC clock pair.
Cpmplement clock of differential SRC clock pair.
Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
Stops all CPU Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up
strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function
as follows:
0= CPU_STOP#
1 = SRC5
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up
strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function
as follows:
0= PCI_STOP#
1 = SRC5#
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.
34
35
36
SRCT10
SRCC10
VDDSRC_IO
OUT
OUT
PWR
37
CPU_STOP#/SRCC5
I/O
38
PCI_STOP#/SRCT5
I/O
39
40
41
42
VDDSRC
SRCC6
SRCT6
GNDSRC
PWR
OUT
OUT
PWR
VDD pin for SRC internal circuits, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte
6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of
SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte
6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
Complement clock of low power differential CPU2/Complement clock of differential SRC pair.
The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on
powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is
as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
43
SRCC7/CR#_E
I/O
44
SRCT7/CR#_F
I/O
45
VDDSRC_IO
PWR
46
CPUC2_ITP/SRCC8
OUT
47
CPUT2_ITP/SRCT8
OUT
48
NC
N/A
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