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參數(shù)資料
| 型號： | ICSLV810FIT |
| 英文描述： | Buffer/Clock Driver |
| 中文描述： | 緩沖器/時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | ICSLV810FIT |
Buffer/Clock Driver
MDS LV810 F
7
Revision 101305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICSLV810
AC Electrical Characteristics—Bank B
VDDB = 2.5 V
, Ambient Temperature -40
°
C to +85
°
C, unless otherwise noted
Parameter
Symbol
Output Skew: skew between
outputs of same package
Pulse Skew: skew between
opposite transitions of same
output (t
PLH
-t
PHL
)
Propagation Delay
t
pLH
/ t
pHL
Conditions
C
L
= 3 pF, R
L
= 500
Figure 3
C
L
= 3 pF, R
L
= 500
Figure 4
Min.
-200
Typ.
Max.
200
Units
ps
t
SK(0
)
t
SK(P)
-200
200
ps
C
L
= 3 pF, R
L
= 500
,
VDDB = 1.5 V
Figure 2
C
L
= 3 pF, R
L
= 500
,
VDDB = 2.5 V
Figure 2
C
L
= 3 pF, R
L
= 500
VDDB = 1.5 V
Figure 5
C
L
= 3 pF, R
L
= 500
VDDB = 2.5 V
Figure 5
C
L
= 3 pF, R
L
= 500
VDDB = 1.5 V
C
L
= 3 pF, R
L
= 500
VDDB = 2.5 V
C
L
= 3 pF, R
L
= 500
VDDB = 1.5 V
C
L
= 3 pF, R
L
= 500
VDDB = 2.5 V
All Outputs,
VDDB = 1.5 V
All Outputs,
VDDB = 2.5 V
CL = 3 pF,
RL = 500
5.5
ns
1.5
2.6
3.5
ns
Part to Part Skew
-1
1
ns
-650
650
ps
Output Rise Time
20% to 80%
t
r(o)
1.0
ns
0.8
ns
Output Fall Time
80% to 20%
t
f(o)
1.0
ns
0.8
ns
Additive Jitter
t
J
34
ps
50
ps
Duty Cycle
Measured at VDD/2
Duty Cycle, VDDB = 1.8V
Output Frequency Range
DC
45
55
%
DC
40
1
50
60
133
%
MHz
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