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參數(shù)資料
| 型號(hào)： | ICSSSTU32864YHT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | MO-205CC, LFBGA-96 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 110K |
| 代理商： | ICSSSTU32864YHT |
8
ICSSSTU32864
0727C—04/15/04
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
300
MHz
0.75
ns
0.9
ns
Hold time, fast slew rate
2, 4
0.50
ns
Hold time, slow slew rate
3, 4
0.70
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V
UNITS
PARAMETERS
Data before CLK
↑, CLK#↓
Data after CLK
↑, CLK#↓
Setup time
SYMBOL
tS
Th
Notes:
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
TYP
MAX
fmax
270
MHz
tPDM
1
CLK, CLK#
Q
1.41
1.85
ns
tPDMSS
2
CLK, CLK#
Q
tphl
RESET#
Q
3
ns
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
SYMBOL
VDD = 1.8V ±0.1V
UNITS
From
(Input)
To
(Output)
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN
MAX
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
V/ns
dV/dt_
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
VDD = 1.8V ± 0.1V
UNIT
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