參數(shù)資料
型號(hào)： ICSSSTUB32871AzLFT
英文描述： 27-Bit Registered Buffer for DDR2
中文描述： 27位注冊(cè)緩沖DDR2內(nèi)存
文件頁(yè)數(shù)： 15/18頁(yè)
文件大?。?/td> 213K
代理商： ICSSSTUB32871AZLFT
15
1186G—04/16/07
ICSSSTUB32871A
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (V
DD
= 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR
Z
o
= 50
; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
Ω
10 MHz;
(1) C
L
includes probe and jig capacitance.
Figure 28 — Load circuit, error output measurements
—
—
—
C
= 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Test Point
DUT
Out
R
L
= 1K
V
DD
LVCMOS
RST
Input
PLH
t
Output
Waveform 2
CC
V
/2
0.15 V
CC
V
0 V
OH
V
0 V
Figure 29
Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Timing
Inputs
Output
Waveform 1
PHL
t
ICR
V
CC
V
/2
ICR
V
VI(PP)
CC
V
OL
V
Timing
Inputs
Output
Waveform 2
PHL
t
ICR
V
ICR
V
VI(PP)
OH
V
V
0
0.15 V
Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
Figure 30
Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
Figure 31
_ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _
Ω
相關(guān)PDF資料
PDF描述
ICSSSTUB32871AzT 27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 28-Bit Registered Buffer for DDR2
ICSSSTUBF32866A 25-Bit Configurable Registered Buffer for DDR2
ICSSSTUBF32866Az(LF)T 25-Bit Configurable Registered Buffer for DDR2
ICSSSTUF32864A 25-Bit Configurable Registered Buffer for DDR2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTUB32871AZT 制造商:ICS 制造商全稱(chēng):ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 制造商:ICS 制造商全稱(chēng):ICS 功能描述:28-Bit Registered Buffer for DDR2
ICSSSTUBF32866A 制造商:ICS 制造商全稱(chēng):ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
ICSSSTUBF32866AZ(LF)T 制造商:ICS 制造商全稱(chēng):ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
ICSSSTUF32864A 制造商:ICS 制造商全稱(chēng):ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
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