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參數(shù)資料
| 型號(hào)： | ICT49FCT3805SO |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS BUFFER/CLOCK DRIVER |
| 中文描述： | 3.3V的CMOS緩沖器/時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大小： | 71K |
| 代理商： | ICT49FCT3805SO |
6
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
D.U.T.
V
IN
V
OUT
V
CC
R
T
Pulse
Generator
50pF
500
500
6V
GND
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
3V
0V
V
OH
t
PLH
t
PHL
V
OL
1.5V
1.5V
t
R
t
F
2.0V
0.8V
INPUT
OUTPUT
t
PLH
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
t
SK(p)
=
|t
PHL -
t
PLH
|
INPUT
OUTPUT
t
PLH1
OUTPUT 1
OUTPUT 2
t
SK(o)
t
PLH2
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT
t
PHL1
t
PHL2
t
SK(o)
t
SK(o)
=
|t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
Output Skew - t
SK(O)
INPUT
t
PLH1
PACKAGE 1
OUTPUT
t
SK(t)
t
PLH2
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
PHL1
t
PHL2
t
SK(t)
t
SK(t)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
PACKAGE 2
OUTPUT
Package Delay
TEST CIRCUITS AND WAV EFORMS
Pulse Skew - t
SK(P)
Test Circuits for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termnation resistance: should be equal to Z
OUT
of the Pulse Generator.
Test
Switch
6V
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
GND
SWITCH POSITION
Output Skew - t
SK(X)
Package Skew - t
SK(T)
NOTES:
1. Diagramshown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
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| ICT49FCT3805SOG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS BUFFER/CLOCK DRIVER |
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