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參數(shù)資料
| 型號(hào)： | ICXO58CL |
| 英文描述： | AREA CCD IMAGE ARRAY |
| 中文描述： | 面陣CCD的圖像陣列 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 203K |
| 代理商： | ICXO58CL |
– 2 –
ICX058CL
Substrate voltage SUB – GND
Supply voltage
Vertical clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
φ
1
, H
φ
2
– V
φ
4
H
φ
1
, H
φ
2
, LH
φ
1
, RG, V
GG
– GND
H
φ
1
, H
φ
2
, LH
φ
1
, RG, V
GG
– SUB
V
L
– SUB
V
φ
1
, V
φ
2
, V
φ
3
, V
φ
4,
V
DD
, V
OUT
– V
L
RG – V
L
V
GG
, V
SS
, H
φ
1
, H
φ
2
, LH
φ
1
– V
L
Storage temperature
Operating temperature
1
+27V (Max.) when clock width < 10μs, clock duty factor < 0.1%.
Block Diagram and Pin Configuration
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note)
Note) : Photo sensor
V
O
V
S
V
G
G
V
φ
1
V
φ
2
V
φ
3
V
φ
4
V
D
G
S
V
L
R
L
φ
1
H
φ
1
H
φ
2
Horizontal register
V
Pin No.
1
2
3
4
5
6
7
8
V
φ
4
V
φ
3
V
φ
2
V
φ
1
GND
V
GG
V
SS
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate bias
Output amplifier source
Signal output
9
10
11
12
13
14
15
16
V
DD
GND
SUB
V
L
RG
LH
φ
1
H
φ
1
H
φ
2
Output amplifier drain supply
GND
Substrate (Overflow drain)
Protective transistor bias
Reset gate clock
Horizontal register final stage transfer clock
Horizontal register transfer clock
Horizontal register transfer clock
Symbol
Description
Pin No.
Description
Pin Description
Absolute Maximum Ratings
–0.3 to +55
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
1
V
DD
, V
OUT,
V
SS
– GND
V
DD
, V
OUT,
V
SS
– SUB
V
φ
1
, V
φ
2
, V
φ
3
, V
φ
4
– GND
V
φ
1
, V
φ
2
, V
φ
3
, V
φ
4
– SUB
Item
Ratings
Unit
Remarks
Symbol
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