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參數(shù)資料
| 型號(hào)： | ICXO58CL |
| 英文描述： | AREA CCD IMAGE ARRAY |
| 中文描述： | 面陣CCD的圖像陣列 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 203K |
| 代理商： | ICXO58CL |
– 4 –
ICX058CL
Clock Voltage Conditions
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
φ
V
| V
VH1
– V
VH2
|
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
φ
H
,V
φ
LH
V
HL
,V
LHL
V
φ
RG
V
RGLH
– V
RGLL
V
φ
SUB
14.55
–0.05
–0.2
–9.0
7.8
–0.25
–0.25
4.75
–0.05
4.5
22.5
15.0
0
0
–8.5
8.5
5.0
0
5.0
23.5
15.45
0.05
0.05
–8.0
9.05
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
24.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
φ
V
= V
VH
n–V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
5
5
6
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
5
The horizontal final stage transfer clock input pin LH
φ
1
is connected to the horizontal transfer clock input
pin H
φ
1
.
6
The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications
are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image
sensor has not significance.
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Item
Symbol
V
RGL
V
φ
RG
Min.
Typ.
Max.
Unit
Waveform
diagram
–0.2
8.5
0
9.0
0.2
9.5
V
V
4
4
Remarks
Reset gate clock
voltage
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