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參數(shù)資料
| 型號(hào)： | ID82C52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Serial Controller Interface |
| 中文描述： | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁(yè)數(shù)： | 8/19頁(yè) |
| 文件大?。?/td> | 255K |
| 代理商： | ID82C52 |
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5-8
Bit 0, which corresponds to D0 at the data bus, is always the
first serial data bit transmitted. Provision is made for the
transmitter parity to be the same or different from the
receiver. The TBRE output pin and flag (USR register) reflect
the status of the TBR. The TC flag (USR register) indicates
when both TBR and TR are empty.
82C52 Interrupt Structure
The 82C52 has provisions for software masking of interrupts
generated for the INTR output pin. Two control bits in the
MCR register, MIEN and INTEN, control modem status inter-
rupts and overall 82C52 interrupts respectively. Figure 9
illustrates the logical control function provided by these sig-
nals.
The modem status inputs (DSR and CTS) will trigger the
edge detection circuitry with any change of status. Reading
the MSR register will clear the detect circuit but has no effect
on the status bits themselves. These status bits always
reflect the state of the input pins regardless of the mask con-
trol signals. Note that the state (high or low) of the status bits
are inverted versions of the actual input pins.
The edge detection circuits for the USR register signals will
trigger only for a positive edge (true assertion) of these sta-
tus bits. Reading the USR register not only clears the edge
detect circuit but also clears (sets to 0) all of the status bits.
The output pins associated with these status bits are not
affected by reading the USR register.
A hardware reset of the 82C52 sets the TC status bit in the
USR. When interrupts are subsequently enabled an interrupt
can occur due to the fact that the positive edge detection cir-
cuitry in the interrupt logic has detected the setting of the TC
bit. If this interrupt is not desired the USR should be read
prior to enabling interrupts. This action resets the positive
edge detection circuitry in the interrupt control logic (Figure 9).
NOTE: For USR and MSR, the setting of status bits is inhibited
during status register READ operations. If a status condition is gen-
erated during a READ operation, the status bit is not set until the trail-
ing edge of the RD pulse.
If the bit was already set at the time of the READ operation, and the
same status condition occurs, that status bit will be cleared at the
trailing edge of the RD pulse instead of being set again.
Software Reset
A software reset of the 82C52 is a useful method for
returning to a completely known state without exercising a
complete system reset. Such a reset would consist of writing
to the UCR, BRSR and MCR registers. The USR and RBR
registers should be read prior to enabling interrupts in order
to clear out any residual data or status bits which may be
invalid for subsequent operation.
Crystal Operation
The 82C52 crystal oscillator circuitry is designed to operate
with a fundamental mode, parallel resonant crystal. This cir-
cuit is the same one used in the Intersil 82C84A clock gener-
ator/driver. To summarize, Table 3 and Figure 10 show the
required crystal parameters and crystal circuit configuration
respectively.
When using an external clock source, the IX input is driven
and the OX output is left open. Power consumption when
using an external clock is typically 50% of that required when
using a crystal. This is due to the sinusoidal nature of the
drive circuitry when using a crystal.
82C52 - 80C86 Interfacing
The following example (Figure 11) shows the interface for an
82C52 in an 80C86 system.
Use of the Intersil CMOS Interrupt Controller (82C59A) is
optional and necessary only if an interrupt driven system is
desired.
By using the Intersil CMOS 82C84A clock generator, the
system can be built with a single crystal providing both the
processor clock and the clock for the 82C52. The 82C52 has
special divider circuitry which is designed to supply industry
standard baud rates with a 2.4576MHz input frequency.
Using a 15MHz crystal as shown, results in less than a 2%
frequency error which is adequate for many applications. For
more precise baud rate requirements, a 14.7456MHz crystal
will drive the 80C86 at 4.9MHz and provide the 82C52 with
the standard baud rate input frequency of 2.4576MHz. If
baud rates above 156Kbaud are desired, the OSC output
can be used instead of the PCLK (
÷
6) output for asynchro-
nous baud rates up to 1Mbaud.
FIGURE 9. 82C52 INTERRUPT STRUCTURE
RD (MSR)
RBRK, TC
OE, FE, PE
(USR)
RD (USR)
DSR, CTS
(MSR)
INTR
PIN 24
INTEN
(MCR)
MIEN
(MCR)
POS.
EDGE
DETECT
POS. OR
NEG.
EDGE
DETECT
TABLE 3.
PARAMETER
TYPICAL CRYSTAL
SPECIFICATION
Frequency
1.0 to 16MHz
Type of Operation
Parallel Resonant, Fundamental Mode
Load Capacitance (CL)
20 or 32pF (Typ)
R
SERIES
(Max)
100
(f = 16MHz, CL = 32pF)
200
(f = 16MHz, CL = 20pF)
NOTE: C1 = C2 = 20pF For CL = 20pF
C1 = C2 = 47pF For CL = 32pF
FIGURE 10.
C1 (NOTE)
GND
C2 (NOTE)
IX
OX
82C52
82C52
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