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參數(shù)資料
| 型號： | ID82C59A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONTROLLER INTERRUPT 28-DIP |
| 標(biāo)準(zhǔn)包裝： | 143 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-CDIP 熔接密封，帶窗口 |
| 包裝： | 管件 |
14
FN2784.5
March 17, 2006
The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine), the
82C59A would have inhibited all lower priority requests with
no easy way for the routine to enable them.
That is where the Special Mask Mode comes in. In the
Special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts
from all other levels (lower as well as higher) that are not
masked.
Thus, any interrupts may be selectively enabled by loading
the mask register.
The Special Mask Mode is set by OCW3 where: ESMM = 1,
SMM = 1, and cleared where ESMM = 1, SMM = 0.
Poll Command
In this mode, the INT output is not used or the
microprocessor internal Interrupt Enable flip flop is reset,
disabling its interrupt input. Service to devices is achieved by
software using a Poll command.
The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD pulse to the 82C59A (i.e., RD =
0, CS = 0) as an interrupt acknowledge, sets the appropriate
IS bit if there is a request, and reads the priority level.
Interrupt is frozen from WR to RD.
The word enabled onto the data bus during RD is:
W0 - W2: Binary code of the highest priority level request-
ing service.
I:
Equal to a “1” if there is an interrupt.
This mode is useful if there is a routine command common to
several levels so that the INTA sequence is not needed
(saves ROM space). Another application is to use the poll
mode to expand the number of priority levels to more than 64.
D7
D6
D5
D4
D3
D2
D1
D0
I
----
W2
W1
W0
EDGE
SENSE
LATCH
LTIM BIT
0 = EDGE
1 = LEVEL
VCC
IR
8080/85
MODE
80C86/
88/286
MODE
INTA
FREEZE
INTA
FREEZE
READ
IRR
WRITE
MASK
READ IMR
READ ISR
MASTER CLEAR
MASK LATCH
REQUEST
LATCH
IN - SERVICE
LATCH
NON-
MASKED
REQ
CLR
Q
SET
TO OTHER PRIORITY CELLS
PRIORITY
RESOLVER
CONTROL
LOGIC
SET ISR
CLR ISR
ISR BIT
Q
D
C
CLR
Q
D
CQ
CLR
SET
Q
NOTES:
1. Master clear active only during ICW1.
2. FREEZE is active during INTA and poll sequence only.
3. Truth Table for D-latch.
C
D
Q
Operation
1D1
D1
Follow
0X
Qn-1
Hold
82C59A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ID82C59A | 制造商:Intersil Corporation 功能描述:Controller IC Package/Case:28-CDIP |
| ID82C59A/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interrupt Controller |
| ID82C59A10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| ID82C59A-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ID82C59A-12 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
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