參數(shù)資料
型號(hào)： IDT54FCT2573CTSOB
廠商： Integrated Device Technology, Inc.
英文描述： CAP 0.047UF 50V 10% X7R SMD-1206 TR-7-PL SN-NIBAR
中文描述： 快速CMOS八路透明鎖存
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 182K
代理商： IDT54FCT2573CTSOB
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.12
7
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2564 lnk 13
2564 drw 09
2564 drw 10
2564 drw 11
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
2564 drw 13
2564 drw 12
相關(guān)PDF資料
PDF描述
IDT54FCT2573DTD FAST CMOS OCTAL TRANSPARENT LATCHES
IDT54FCT2573DTDB FAST CMOS OCTAL TRANSPARENT LATCHES
IDT54FCT2573DTE CAP 0.047UF 100V 20% X7R SMD-1206 TR-7-PL SN-NIBAR
IDT54FCT2573DTEB FAST CMOS OCTAL TRANSPARENT LATCHES
IDT54FCT2573DTL FAST CMOS OCTAL TRANSPARENT LATCHES
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