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參數(shù)資料
| 型號： | IDT54FCT388915T133PYB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, SSOP-28 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | IDT54FCT388915T133PYB |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
9
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
PLL
2f
PLL
2f
CPU
CARD
CPU
CARD
CLOCK
@f
SYSTEM
CLOCK
SOURCE
FCT388915T
FCT388915T
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
MEMORY
CONTROL
PLL
2f
MEMORY
CARDS
CLOCK @2f
at point of use
FCT388915T
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication
and Low Board-to-Board skew
FCT388915T System Level Testing Functionality
When the PLL_EN pin is LOW, the PLL is bypassed and the
FCT388915T is in low frequency "test mode". In test mode
(with FREQ_SEL HIGH), the 2Q output is inverted from the
selected SYNC input, and the Q outputs are divide-by-2
(negative edge triggered) of the SYNC input, and the Q/2
output is divide-by-4 (negative edge triggered). With
FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,
the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A
recommended test configuration would be to use SYNC0 or
SYNC1 as the test clock input, and tie PLL_EN and REF_SEL
together and connect them to the test select logic.
This functionality is needed since most board-level testers
run at 1 MHz or below, and theFCT 388915T cannot lock onto
that low of an input frequency. In the test mode described
above, any test frequency test can be used.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T133PYB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70 | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70 | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT533DB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
| IDT54FCT573ADB | 制造商:Integrated Device Technology Inc 功能描述: |
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