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參數(shù)資料
| 型號(hào)： | IDT54FCT388915T70 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | 3.3V的低歪曲基于PLL的CMOS時(shí)鐘驅(qū)動(dòng)器，（3態(tài)） |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大小： | 145K |
| 代理商： | IDT54FCT388915T70 |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
2
PIN CONFIGURATIONS
PLCC/LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
SSOP
TOP VIEW
3052 drw 03
5
6
7
8
9
10
11
V
CC
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
1
2
3
4
20
19
18
17
16
15
14
13
Q4
V
CC
2Q
12
GND
Q5
Q/2
GND
Q3
V
CC
LF
Q2
GND
LOCK
GND(AN)
SO28-7
21
22
23
24
SYNC(1)
FREQ_SEL
GND
Q0
V
CC
Q1
GND
PLL_EN
25
26
27
28
O
V
C
Q
G
Q
V
C
2
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
P
G
Q
V
C
Q
G
F
FEEDBK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
SYNC(1)
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J28-1,
L28-1
3052 drw 02
I/O
I
I
Description
Reference clock input.
Reference clock input.
REF_SEL
FREQ_SEL
FEEDBACK
I
I
I
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between
÷
1 and
÷
2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
LF
Q0-Q4
Q5
I
Input for external loop filter connection.
Clock output.
Inverted clock output.
O
O
2Q
Q/2
LOCK
O
O
O
Clock output (2 x Q frequency).
Clock output (Q frequency
÷
2).
Indicates phase lock has been achieved (HIGH when locked).
OE/
RST
I
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
PLL_EN
I
3052 tbl 01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT388915T70J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70JB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70JB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT533DB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
| IDT54FCT573ADB | 制造商:Integrated Device Technology Inc 功能描述: |
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