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參數(shù)資料
| 型號(hào)： | IDT5T905PGGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5T SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | GREEN, TSSOP-28 |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大小： | 108K |
| 代理商： | IDT5T905PGGI |
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INDUSTRIALTEMPERATURERANGE
IDT5T905
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER
3
PIN DESCRIPTION
Symbol
I/O
Type
Description
A
I
Adjustable(1)
Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input.
A/VREF
I
Adjustable(1)
Complementary clock input.
A/VREF is the "complementary" side of A if the input is in differential mode. If operating in single-ended
mode,
A/VREF is connected to GND. For single-ended operation in differential mode, A/VREF should be set to the desired toggle
voltage for A:
2.5V LVTTL
VREF = 1250mV
1.8V LVTTL, eHSTL
VREF = 900mV
HSTL
VREF = 750mV
LVEPECL
VREF = 1082mV
G
I
LVTTL(5)
Gate control for Qn outputs. When
G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously
disabled to the level designated by GL(4).
GL
I
LVTTL(5)
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Qn
O
Adjustable(2)
Clock outputs
RxS
I
3 Level(3)
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input
TxS
I
3 Level(3)
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in
conjunction with VDDQ to set the interface levels.
VDD
PWR
Power supply for the device core and inputs
VDDQ
PWR
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be connected to VDD.
GND
PWR
Power supply return for all power
NOTES:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3 level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
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