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參數(shù)資料
| 型號： | IDT5T9304PGGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | GREEN, TSSOP-24 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 666K |
| 代理商： | IDT5T9304PGGI |
IDT5T9304
2.5V LVDS 1:4 CLOCK BUFFER TERABUFFER II
PRELIMINARY
IIDT LVDS CLOCK BUFFER TERABUFFER II
3
IDT5T9304 REV. A JULY 23, 2007
Table 1. Pin Descriptions
NOTES:
1.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
4.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz))
NOTE: This parameter is measured at characterization but not tested.
Name
Type
Description
A[1:2]
Input
Adjustable (1, 4)
Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2]
Input
Adjustable (1, 4)
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For
LVTTL single-ended operation, A[1:2] should be set to the desired toggle
voltage for A[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
G
Input
LVTTL
Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G is
LOW, the differential outputs are active. When G is HIGH, the differential
outputs are asynchronously driven to the level designated by GL(2).
GL
Input
LVTTL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and
"complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and
"complementary" outputs disable HIGH.
Q[1:4]
Output
LVDS
Clock outputs.
Q{1:4}
Output
LVDS
Complementary clock outputs.
SEL
Input
LVTTL
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects
A1 and A1.
PD
Input
LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into low
power mode. Inputs and outputs are disabled. Both "true" and
"complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)
VDD
Power
Power supply for the device core and inputs.
GND
Power
Power supply return for all power.
nc
No connect; recommended to connect to GND.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
3pF
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