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參數(shù)資料
| 型號： | IDT5V9352 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| 中文描述： | 3.3V/2.5V鎖相環(huán)時鐘驅(qū)動器零延遲緩沖器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 81K |
| 代理商： | IDT5V9352 |
1
INDUSTRIAL TEMPERATURE RANGE
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
÷
6
÷
4
÷
2
÷
2
VCO
1
0
1
0
CCLK
Q
B
3
Q
B
0
Q
B
1
Q
B
2
Q
A
0
Q
A
1
Q
A
2
Q
A
3
Q
A
4
Q
C
1
Q
C
0
1
0
BANK A
BANK B
BANK C
1
0
1
0
PLL_En
REFCLK
FBIN
VCO_
SEL
f
SELA
f
SELB
MR/OE
f
SELC
PLL
REF
FB
AUGUS T 2003
2003 Integrated Device Technology, Inc.
DSC 5973/18
c
IDT5V9352
INDUS T RIAL T E MPE RAT URE RANGE
3.3V/2.5V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
precisely align, in both frequency and phase. The 5V9352 operates at 2.5V
and 3.3V.
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1.
The output frequency relationship is controlled by the f
SEL
frequency
control pins. The f
SEL
pins, as well as other inputs, are LVCMOS/LVTTL
compatible inputs
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
mnimzing component count, board space, and cost.
Because it is based on PLL circuitry, the 5V9352 requires a stabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the
PLL_EN
to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-lock loop clock distribution for high performance clock
tree applications
Output enable bank control
External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
No external RC network required for PLL loop stability
Operates at 3.3V/2.5V V
CC
Spread Spectrum Compatible
Operating frequency up to 200MHz
Compatible with Motorola MPC9352
Available in 32-pin TQFP package
相關(guān)PDF資料 |
PDF描述 |
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| IDT5V9352PRI | 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| IDT5V9910A-7SOI | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
| IDT5V9910A-5SOI | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
| IDT5V9910A-7SO | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
| IDT5V9910A | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9352PFGI | 功能描述:IC BUFFER ZD PLL CLK DVR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V9352PFGI8 | 功能描述:IC BUFFER ZD PLL CLK DVR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V9855-003PFI | 制造商:INT_DEV_TECH 功能描述: |
| IDT5V9885ANLGI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT5V9885BNLGI | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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