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參數(shù)資料
| 型號： | IDT5V9352 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| 中文描述： | 3.3V/2.5V鎖相環(huán)時鐘驅動器零延遲緩沖器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 81K |
| 代理商： | IDT5V9352 |
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
PIN DESCRIPTION
Terminal
Name
REFCLK
FBIN
V
CCA
GND
7, 13, 17, 24,
No.
6
8
10
Type
I
I
PWR
Ground
Description
Reference clock input
Feedback input.
Analog power supply
Negative power supply
28, 29
1
5
12, 14, 15,
18, 19
22, 23, 26, 27
30, 31
11, 16, 20, 21,
25, 32
9
2, 3, 4
VCO_
SEL
MR/
OE
Q
A (0:4)
I
I
Allows for the choice of two VCO ranges to optimze PLL stability and jitter performance
Allows the user to force the outputs into HIGH impedence for board level test
Q
B (0:3)
Q
C (0:1)
V
CC
O
Clock outputs. These outputs provide low skew copies of REFCLK or can be at different frequencies than REFCLK.
PWR
Positive power supply for I/O and core
PLL_EN
f
SEL(C:A)
I
I
PLL enable input. When set LOW, PLL is enabled. When set HIGH, PLL is disabled.
Frequency control pin
FUNCTION TABLES
f
SELA
Q
A
n
0
÷
4
1
÷
6
NOTE:
1. IDT5V9352 requires reset at power up and after any loss of PLL lock. Length of reset
pulse should be greater than two REF CLK cycles (REFCLK).
f
SELB
0
1
Q
B
n
÷
4
÷
2
f
SELC
0
1
Q
C
n
÷
2
÷
4
Control Pin
VCO_
SEL
MR/
OE
Logic 0
fVCO
Output Enable
Logic 1
fVCO / 2
Outputs disable (high-impedance state) and
reset of the device.
Disable PLL
PLL_En
Enable PLL
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C, V
CC
= 3.3V ± 5%
NOTES:
1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
2. Inputs have pull-down resistors affecting the input current.
3. Icc is the DC current consumption of the device with all outputs open in high-impedance state and the inputs in its default state or open.
Parameter
V
IH
V
IL
V
OH
V
OL
Description
Test Conditions
Min.
2
Typ.
(1)
Max.
V
CC +
0.3
0.8
Unit
V
V
V
V
Input HIGH Level
Input LOW Level
HIGH Level Output Voltage
LOW Level Output Voltage
I
OH
= –24mA
I
OL
= 12mA
I
OL
= 24mA
2.4
0.3
0.55
Z
OUT
I
I
I
CC
I
CCA
Output Impedance
Input Current
(2)
MaximumQuiescent Supply Current
(3)
PLL Supply Current
14 - 17
μA
mA
mA
V
I
= V
CC
or GND
All V
CC
pins
V
CCA
pin
±200
1
5
3
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| IDT5V9352PRI | 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
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| IDT5V9910A-5SOI | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
| IDT5V9910A-7SO | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
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