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參數(shù)資料
| 型號(hào)： | IDT5V991A-2JG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | LEAD FREE, PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | IDT5V991A-2JG |
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
EX TERNAL FEEDBACK
By providing external feedback, the IDT5V991A gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determned by the nomnal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide mnimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
FS = LOW
1/(44 x F
NOM
)
15 to 35MHz
FS = MID
1/(26 x F
NOM
)
25 to 60MHz
FS = HIGH
1/(16 x F
NOM
)
40 to 85 MHz
Comments
Timng Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±9.09ns
±49o
±14%
t
U
= 1.52ns
t
U
= 0.91ns
t
U
= 0.76ns
—
—
—
±9.23ns
±83o
±23%
—
t
U
= 1.54ns
t
U
= 1.28ns
t
U
= 0.96ns
t
U
= 0.77ns
—
±9.38ns
±135o
±37%
—
—
—
t
U
= 1.56ns
t
U
= 1.25ns
t
U
= 0.78ns
ns
Phase Degrees
% of Cycle Time
Example 1, F
NOM
= 15MHz
Example 2, F
NOM
= 25MHz
Example 3, F
NOM
= 30MHz
Example 4, F
NOM
= 40MHz
Example 5, F
NOM
= 50MHz
Example 6, F
NOM
= 80MHz
PLL PROGRAMMABLE SK EW RANGE AND RESOLUTION TABLE
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
Skew (Pair #1, #2)
LL
(1)
LM
LH
ML
MM
Zero Skew
MH
HL
HM
HH
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
Skew (Pair #4)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Inverted
(2)
–4t
U
–3t
U
–2t
U
–1t
U
1t
U
2t
U
3t
U
4t
U
NOTES:
1.
2.
LL disables outputs if TEST = MID and GND/
sOE
= HIGH.
When pair #4 is set to HH (inverted), GND/
sOE
disables pair #4 HIGH when V
CCQ
/PE = HIGH, GND/
sOE
disables pair #4 LOW when V
CCQ
/PE = LOW.
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