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參數(shù)資料
| 型號(hào)： | IDT5V993A-7QI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 76K |
| 代理商： | IDT5V993A-7QI8 |
2
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
Supply Voltage to Ground
–0.5 to +7
V
VI
DC Input Voltage
–0.5 to VCC+0.5
V
REF Input Voltage
–0.5 to +5.5
V
Maximum Power Dissipation (TA = 85°C)
0.66
W
TSTG
Storage Temperature
–65 to +150
° C
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
CAPACITANCE(TA=+25°C,f=1MHz,V
IN
= 0V)
Parameter
Description
Typ.
Max.
Unit
CIN
InputCapacitance
4
6
pF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RE F
FS
3F0
3F1
4Q1
4Q0
GND
3Q1
3Q0
FB
GND
TE ST
2F1
2F0
GND/sO E
1F1
1F0
V CCN
1Q0
1Q1
GND
2Q0
2Q1
VCCN
V CCQ/P E
VCCQ
QSOP
TOP VIEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
PROGRAMMABLESKEW
PIN DESCRIPTION
Pin Name
Type
Description
REF
I N
Reference Clock Input
FB
I N
FeedbackInput
TEST(1)
I N
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control
Summary Table) remain in effect. Set LOW for normal operation.
GND/
sOE(1)
I N
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and GND/
sOE isHIGH,thenF[1:0]pinsactasoutputdisable
controls for individual banks when nF[1:0] = LL. Set GND/
sOE LOW for normal operation.
VCCQ/PE
I N
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
referenceclock.
nF[1:0]
I N
3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS
I N
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
nQ[1:0]
OUT
Three output banks of two outputs with programmable skew (1Q:3Q), and 4Q output has fixed zero skew outputs.
VCCN
PWR
Power supply for output buffers
VCCQ
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
NOTE:
1. When TEST = MID and GND/
sOE = HIGH, PLL remains active.
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