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參數(shù)資料
| 型號： | IDT5V994JI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 80K |
| 代理商： | IDT5V994JI8 |
3
INDUSTRIALTEMPERATURERANGE
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
NOTE:
1. When TEST = MID and
sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
PIN DESCRIPTION
Pin Name
Type
Description
REF
I N
Reference Clock Input
FB
I N
FeedbackInput
TEST(1)
I N
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
sOE(1)
I N
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE is HIGH, the nF[1:0] pins act as output disable
controls for individual banks when nF[1:0] = LL. Set
sOE LOW for normal operation.
PE
I N
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock.
nF[1:0]
I N
3-level inputs for selecting 1 of 9 skew taps or frequency functions
nQ[1:0]
OUT
Four banks of two outputs with programmable skew
VDDQ
PWR
Power supply for output buffers
VDD
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
EXTERNALFEEDBACK
By providing external feedback, the IDT5V994 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
NOTES:
1. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs
will be FNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication
by using a divided output as the FB input. Using the nF[1:0] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).
2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
Comments
Timing Unit Calculation (tU)
1/(16 x FNOM)
VCO Frequency Range (FNOM)(1,2)
70 to 133MHz
Skew Adjustment Range(2)
Max Adjustment:
±5.36ns
ns
±135°
Phase Degrees
±37.5%
% of Cycle Time
Example 1, FNOM = 80MHz
tU = 0.78ns
Example 2, FNOM = 100MHz
tU = 0.63ns
Example 3, FNOM = 133MHz
tU = 0.47ns
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
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