參數(shù)資料
型號: IDT5V9955
廠商: Integrated Device Technology, Inc.
英文描述: Scan Test Devices With 18-Bit Bus Transceivers And Registers 64-LQFP -40 to 85
中文描述: 3.3V的可編程相偏雙PLL時鐘驅(qū)動器TURBOCLOCK糯
文件頁數(shù): 6/11頁
文件大小: 129K
代理商: IDT5V9955
6
INDUSTRIAL TEMPERATURE RANGE
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
I
DDQ
Quiescent Power Supply Current
Test Conditions
(1)
Typ.
(2)
40
Max.
60
Unit
mA
V
DD
= Max., TEST = MID, REF = LOW,
xPE = LOW, x
sOE
= LOW, x
PD
= HIGH
xFS = MID, All outputs unloaded
V
DD
= Max.,
PD
= LOW, x
sOE
= LOW
xPE = HIGH, TEST = HIGH, xFS = HIGH
xnF
[1:0]
= HH, xDS
[1:0]
= HH
V
IN
= 3V, V
DD
= Max., x
PD
= LOW, TEST = HIGH
I
DDPD
Power Down Current
50
μ
A
I
DD
Power Supply Current per Input HIGH
(REF and xFB inputs only)
1
60
μ
A
xFS = L
xFS = M
xFS = H
xFS = L, F
VCO
= 50MHz, C
L
= 0pF
xFS = M F
VCO
= 100MHz, C
L
= 0pF
xFS = H, F
VCO
= 200MHz, C
L
= 0pF
190
150
130
112
160
250
290
230
200
I
DDD
Dynamc Power Supply Current per Output
μ
A/MHz
I
TOT
Total Power Supply Current
mA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Conditions
(1)
Min.
2
V
DD
0.6
V
DD
/2
0.3
5
Max.
0.8
Unit
V
V
V
V
V
μA
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(2)
Input MID Voltage
(2)
Input LOW Voltage
(2)
Input Leakage Current
(REF, xFB Inputs Only)
Guaranteed Logic HIGH (REF, xFB Inputs Only)
Guaranteed Logic LOW (REF, xFB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
or GND
V
DD
= Max.
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
DD
= Max., V
IN
= GND
V
DD
= Max., V
IN
= V
DD
V
DD
= Mn., I
OH
=
2mA (xLOCK Output)
V
DDQ
= Mn., I
OH
=
12mA (xnQ
[1:0]
Outputs)
V
DD
= Mn., I
OL
= 2mA (xLOCK Output)
V
DDQ
= Mn., I
OL
= 12mA (xnQ
[1:0]
Outputs)
V
DD
/2+0.3
0.6
+5
HIGH Level
MID Level
LOW Level
+400
+100
+100
0.4
0.4
I
3
3-Level Input DC Current
(TEST, xFS, xnF
[1:0]
, xDS
[1:0]
)
Input Pull-Up Current (xPE, x
PD
)
Input Pull-Down Current (x
sOE
)
Output HIGH Voltage
100
400
25
2.4
2.4
μA
I
PU
I
PD
V
OH
μA
μA
V
V
OL
Output LOW Voltage
V
NOTES:
1. All conditions apply to A and B banks.
2. These inputs are normally wired to V
DD
, GND, or unconnected. Internal termnation resistors bias unconnected inputs to V
DD
/2. If these inputs are switched, the function and timng
of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limts are achieved.
NOTES:
1. Measurements are for divide-by-1 outputs, xnF
[1:0]
= MM and xDS
[1:0]
= MM All conditions apply to A and B banks.
2. For nomnal voltage and temperature.
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