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參數(shù)資料
| 型號： | IDT5V995PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDT5V995PFI |
1
INDUSTRIAL TEMPERATURE RANGE
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
FEBRUARY 2002
2002 Integrated Device Technology, Inc.
DSC 5851/6
c
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 2MHz to 200MHz
Output frequency: 6MHz to 200MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode
Lock indicator
Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
FS
PE
LOCK
PLL
3
sOE
REF
/ N
3
3
FB
3
3
Skew
Select
Skew
Select
Skew
Select
Skew
Select
3
3
3
3
3
3
1Q
0
1Q
1
1F1:0
2Q
0
2Q
1
2F1:0
DS1:0
3Q
0
3Q
1
3F1:0
4Q
0
4Q
1
4F1:0
PD
TEST
3
IDT5V995
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK II
DESCRIPTION:
The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for
high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5V995 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from1 to 12 through the
use of the DS[1:0] inputs. This provides the user with frequency
multiplication from1 to 12 without using divided outputs for feedback.
When the
sOE
pin is held low, all the outputs are synchronously enabled.
However, if
sOE
is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V995 has
LVTTL outputs with 12mA balanced drive outputs.
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