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參數(shù)資料
| 型號： | IDT5V995 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 3.3V的可編程相偏PLL時鐘驅動器TURBOCLOCK |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 74K |
| 代理商： | IDT5V995 |
2
INDUSTRIAL TEMPERATURE RANGE
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
V
DDQ
, V
DD
Supply Voltage to Ground
V
I
DC Input Voltage
REF Input Voltage
MaximumPower
Dissipation
T
STG
Storage Temperature Range
Max
Unit
V
V
V
W
–0.5 to +4.6
–0.5 to V
DD
+0.5
–0.5 to +5.5
0.7
1.1
–65 to +150
T
A
= 85°C
T
A
= 55°C
°C
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF
[1:0]
, and DS
[1:0]
.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
C
IN
Input Capacitance
Typ.
5
Max.
7
Unit
pF
4F
1
sOE
PE
V
DDQ
4Q
1
4Q
0
GND
PD
V
DDQ
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1F
0
V
DDQ
1Q
0
1Q
1
GND
GND
DS
1
DS
0
V
DDQ
GND
LOCK
3
0
F
V
D
R
G
T
2
1
2
0
4
0
3
1
1
1
G
3
1
3
0
V
D
F
V
D
2
1
2
0
V
D
V
D
G
TQFP
TOP VIEW
NOTE:
1. When TEST = MID and
sOE
= HIGH, PLL remains active
with nF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[
1:0
] = LL.
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
Type
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q
0
and 2Q
1
) in a LOW state (for PE = H) - 2Q
0
and 2Q
1
may
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE
is HIGH, the nF[
1:0
] pins act as output
disable controls for individual banks when nF[
1:0
] = LL. Set
sOE
LOW for normal operation (has internal pull-down).
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
Four banks of two outputs with programmable skew
3-level inputs for feedback divider selection
Power down control. Shuts off entire chip when LOW (has internal pull-up).
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs.
Power supply for output buffers
Power supply for phase locked loop, lock output, and other internal circuitry
Ground
sOE
(1)
IN
PE
IN
nF
[1:0]
FS
nQ
[1:0]
DS
[1:0]
PD
LOCK
IN
IN
OUT
IN
IN
OUT
V
DDQ
V
DD
GND
PWR
PWR
PWR
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