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參數(shù)資料
| 型號： | IDT5V995PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDT5V995PFI |
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timng relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t
U
) which ranges
from625ps to 1.3ns (see Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
to mnimze the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
PROGRAMMABLE SK EW
EX TERNAL FEEDBACK
By providing external feedback, the IDT5V995 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determned by the nomnal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be F
NOM
when the output connected to FB is undivided
and DS[
1:0
] = MM The frequency of the REF and FB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication by using a divided output as the
FB input and setting DS[
1:0
] = MM Using the DS[
1:0
] inputs allows a different method for frequency multiplication (see Divide Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide mnimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
FS = LOW
1/(32 x F
NOM
)
24 to 50MHz
FS = MID
1/(16 x F
NOM
)
48 to 100MHz
FS = HIGH
1/(8 x F
NOM
)
96 to 200MHz
Comments
Timng Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±7.8125ns
±67.5°
±18.75%
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
—
—
±7.8125ns
±135°
±37.5%
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
±7.8125ns
±270°
±75%
—
—
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
ns
Phase Degrees
% of Cycle Time
Example 1, F
NOM
= 25MHz
Example 2, F
NOM
= 37.5MHz
Example 3, F
NOM
= 50MHz
Example 4, F
NOM
= 75MHz
Example 5, F
NOM
= 100MHz
Example 6, F
NOM
= 150MHz
Example 7, F
NOM
= 200MHz
PROGRAMMABLE SK EW RANGE AND RESOLUTION TABLE
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