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參數(shù)資料
| 型號： | IDT5V996BBI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封裝： | PLASTIC, BGA-144 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT5V996BBI8 |
6
INDUSTRIALTEMPERATURERANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
NOTES:
1.
Measured at VTH = VDDQ/2, output load CL = 20pF.
2.
Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3.
tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4.
There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted, and Divided (Divide-by-2 or Divide-by-4 mode).
5.
tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.)
6.
tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD and VDDQ are stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7.
tODCV is measured with nF[2:0] = MMM.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
FNOM
VCO Frequency Range
See PLL Programmable Skew Range and Resolution Table
FREF
REF Clock Input Frequency
25
—
225
MHz
tREF
REF Clock Duty Cycle
10
—
90
%
tU
Programmable Skew Time Unit
See Control Summary Table
tSKEWPR
Matched-Pair Skew (xQ0, xQ1)(1,2,3)
—
150
tSK(0)
Output Skew (Rise-Rise, Fall-Fall, Same Frequency and Phase)(1,2)
—
350
tSK(
ω)
Multiple Frequency Skew(1,2)
—
550
tSK(INV)
Inverting Skew Between Nominal and Inverted(1,2,4)
—
500
tSKEW1
Output Skew (Rise-Fall, Inverted-Divided)(1,2)
—
500
ps
tSKEW4
Output Skew (Rise-Fall, Divided-Divided)(1,2,4)
—
500
tDEV
Device-to-Device Skew(2,5)
—
250
t
φ
REF Input to FB Static Phase Offset (VTH = VDDQ/2)
-250
—
+250
tODCV
Output Duty Cycle Variation from 50%(1,7)
-0.75
—
+0.75
ns
tR
Output Rise Time (0.8V to 2V)(1)
—
2.2
ns
tF
Output Fall Time (2V to 0.8V)(1)
—
2.2
ns
tLOCK
PLL Lock Time(6)
—
0.5
ms
tJ
Cycle-to-Cycle Output Jitter, Peak-to-Peak(1)
—
150
ps
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