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參數(shù)資料
| 型號(hào)： | IDT5V996BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封裝： | PLASTIC, BGA-144 |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | IDT5V996BBI |
8
INDUSTRIALTEMPERATURERANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
AC TIMING DIAGRAM
tJ
RE F
FB
Q
OTH ER Q
INVER TED Q
REF D IVIDE D B Y 2
REF D IVIDE D B Y 4
tREF
tSK(INV)
tSKEW1,4
tSK(ω )
tSK(INV)
tSKEWPR
tSK(O)
tRPW H
tRPW L
tSKEW PR
tSK(O)
t(φ)
tSK(ω )
tSKEW1,4
tSK(ω )
tODCV
tODC V
NOTES:
SE:
The AC Timing Diagram applies to SE=VDD. For SE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75
Ω to VDDQ/2.
tSKEWPR:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSK(0):
The skew between outputs when they are selected for 0tU.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW1 and tSKEW4 specifications.
tSK(
ω):
The skew between outputs of different frequencies.
tSK(INV):
The skew between inverting and non-inverting outputs.
tR and tF are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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