參數(shù)資料
型號: IDT6168LA45SOB
廠商: Integrated Device Technology, Inc.
英文描述: CMOS STATIC RAM 16K (4K x 4-BIT)
中文描述: 16K的的CMOS靜態(tài)RAM(4K的× 4位)
文件頁數(shù): 5/9頁
文件大小: 91K
代理商: IDT6168LA45SOB
6.42
IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit) Military, Industrial, and Commercial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1, 2)
Timing Waveform of Read Cycle No. 2
(1, 3)
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured ±200mV fromsteady state.
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%, All Temperature Ranges)
3090 drw 06
ADDRESS
DATA
OUT
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DATA VALID
,
t
PD
3090 drw 07
DATA
OUT
CS
t
ACS
(4)
t
CLZ
(3)
t
CHZ
t
PU
I
CC
I
SB
SUPPLY
CURRENT
V
CC
t
RC
DATA
OUT
VALID
HIGH IMPEDANCE
HIGH IMPEDANCE
,
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed with AC Test load (Figure 2) by device characterization, but is not production tested.
Symbol
Parameter
6168SA15
(1)
6168SA20
(1)
6168LA20
(1)
6168SA25
6168LA25
6168SA45
(2)
6168LA45
(2)
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
15
____
20
____
25
____
45
____
ns
t
AA
Address Access Time
____
15
____
20
____
25
____
45
ns
t
ACS
Chip Select Access Time
____
15
____
20
____
25
____
45
ns
t
CLZ
(3)
Chip Select to Output in Low-Z
3
____
5
____
5
____
5
____
ns
t
CHZ
(3)
Chip Deselect to Output in High-Z
____
8
____
10
____
10
____
25
ns
t
OH
Output Hold fromAddress Change
3
____
3
____
3
____
3
____
ns
t
PU
(3)
Chip Select to Power Up Time
0
____
0
____
0
____
0
____
ns
t
PD
(3)
Chip Deselect to Power Down Time
____
35
____
20
____
25
____
40
ns
3090 tbl 12
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