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參數(shù)資料
| 型號(hào)： | IDT6168LA45SOB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS STATIC RAM 16K (4K x 4-BIT) |
| 中文描述： | 16K的的CMOS靜態(tài)RAM（4K的× 4位） |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 91K |
| 代理商： | IDT6168LA45SOB |
6.42
IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit) Military, Industrial, and Commercial Temperature Ranges
7
Timing Waveform of Write Cycle No. 2 (
CS
Controlled Timing)
(1,2,5)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured fromthe earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals should not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high impedance state.
6. Transition is measured ±200mV fromsteady state.
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,2,5)
CS
DATA
IN
ADDRESS
WE
DATA
OUT
3090 drw 08
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WHZ
t
OW
(4)
t
AS
(6)
(4)
(6)
DATA VALID
PREVIOUS DATA VALID
DATA
VALID
(3)
t
CHZ
(6)
,
WR
t
CS
3090 drw 09
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
AS
t
DATA VALID
(3)
,
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