參數(shù)資料
型號: IDT7005S70JB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
中文描述: 8K X 8 DUAL-PORT SRAM, 70 ns, PQCC68
封裝: 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68
文件頁數(shù): 5/20頁
文件大小: 265K
代理商: IDT7005S70JB
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
13
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH
BUSY
BUSY (M/S = VIH)(2,4,5)
NOTES:
1. tWH must be met for both
BUSY input (slave) and output (master).
2.
BUSY is asserted on Port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/
S = VIL (slave).
2.
CEL = CER = VIL.
3.
OE = VIL for the reading port.
4. If M/
S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
2738 drw 13
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
2738 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
R/
W"B"
tWH
(2)
(3)
(1)
TIMING WAVEFORM OF WITH WRITE
BUSY
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