參數(shù)資料
型號: IDT7015S35PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Quad Low-Power JFET-Input General-Purpose Operational Amplifier 14-TSSOP 0 to 70
中文描述: 8K X 9 DUAL-PORT SRAM, 35 ns, PQFP80
封裝: TQFP-80
文件頁數(shù): 13/20頁
文件大?。?/td> 263K
代理商: IDT7015S35PF
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.12
13
TIMING WAVEFORM OF READ WITH
BUSY
(M/
S
= V
IH
)
(2,4,5)
2954 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
=V
IL.
2.
CE
L
=
CE
R
= V
IL.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH
BUSY
2954 drw 14
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
( 1 )
(2)
NOTES:
1. t
WH
must be met for both
BUSY
input (SLAVE) and output (MASTER).
2.
BUSY
is asserted on port "B" blocking R/
W
"B", until
BUSY
"B" goes High.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
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IDT7015S35PFB HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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