參數資料
型號: IDT7016L35PFB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Quad Low-Power JFET-Input Operational Amplifier 14-PDIP 0 to 70
中文描述: 16K X 9 DUAL-PORT SRAM, 35 ns, PQFP80
封裝: TQFP-80
文件頁數: 13/20頁
文件大?。?/td> 262K
代理商: IDT7016L35PFB
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.13
13
TIMING WAVEFORM OF READ WITH
BUSY
(M/
S
= V
IH
)
(2,4,5)
3190 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/
S
=V
IL
2.
CE
L
=
CE
R
= V
IL.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH
BUSY
3190 drw 14
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(1)
(2)
NOTES:
1. tWH must be met for both
BUSY
input (SLAVE) and output (MASTER).
2.
BUSY
is asserted on port "B" blocking R/
W
"B", until
BUSY
"B" goes High.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
相關PDF資料
PDF描述
IDT7016S Low-Power JFET-Input Quad Operational Amplifier 20-LCCC -55 to 125
IDT7016S12G Low-Power JFET-Input Quad Operational Amplifier 14-CDIP -55 to 125
IDT7016S12GB Low-Power JFET-Input Quad Operational Amplifier 14-CFP -55 to 125
IDT7016S12J Low-Power JFET-Input Quad Operational Amplifier 20-LCCC -55 to 125
IDT7016S12JB Low-Power JFET-Input Quad Operational Amplifier 20-LCCC -55 to 125
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參數描述
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