參數(shù)資料
型號: IDT7016S15GGB
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM
中文描述: 高速16K的× 9雙端口靜態(tài)RAM
文件頁數(shù): 12/20頁
文件大?。?/td> 173K
代理商: IDT7016S15GGB
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the
Operating Temperature and S upply Voltage Range
(6)
APRIL 04, 2006
NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Waveformof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
Parameter
Min.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time fromAddress Match
____
12
____
15
ns
t
BDA
BUSY
Disable Time fromAddress Not Matched
____
12
____
15
ns
t
BAC
BUSY
Access Time fromChip Enable Low
____
12
____
15
ns
t
BDC
BUSY
Disable Time fromChip Enable High
____
12
____
15
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
15
____
18
ns
t
WH
Write Hold After
BUSY
(5)
11
____
13
____
ns
BUSY
INPUT TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
11
____
13
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
25
____
30
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
20
____
25
ns
3190 tbl 14a
7016X20
Com'l, Ind
& Mlitary
7016X25
Com'l &
Mlitary
7016X35
Com'l &
Mlitary
Symbol
Parameter
Mn.
Max.
Min.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time fromAddress Match
____
20
____
20
____
20
ns
t
BDA
BUSY
Disable Time fromAddress Not Matched
____
20
____
20
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable Low
____
20
____
20
____
20
ns
t
BDC
BUSY
Disable Time fromChip Enable High
____
17
____
17
____
20
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
30
____
30
____
35
ns
t
WH
Write Hold After
BUSY
(5)
15
____
17
____
25
____
ns
BUSY
INPUT TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
15
____
17
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
45
____
50
____
60
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45
ns
3190 tbl 14b
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