- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377261 > IDT7016S15PFG (INTEGRATED DEVICE TECHNOLOGY INC) HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM PDF資料下載
參數(shù)資料
| 型號： | IDT7016S15PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 15 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.4 MM HEIGHT, GREEN, TQFP-80 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 173K |
| 代理商： | IDT7016S15PFG |
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 04, 2006
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. Fromthis it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire systemcan hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timng is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programmng technique, if semaphores are msused
or msinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization programat power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into themat initialization fromboth sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT7016’s Dual-Port RAM Say the 16K x 9 RAM
was to be divided into two 8K x 9 blocks which were to be dedicated at any
one time to servicing either the left or right port. Semaphore 0 could be used
to indicate the side which would control the lower section of memory, and
Semaphore 1 could be defined as the indicator for the upper section of
memory.
To take a resource, in this example the lower 8K of Dual-Port RAM
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and performother tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a simlar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAMwith each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
performanother task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7016 in a separate
memory space fromthe Dual-Port RAM This address space is accessed
by placing a LOW input on the
SEM
pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address,
OE
, and
R/
W
) as they would be used in accessing a standard static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A
0
– A
2
. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D
0
is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location fromthe same side, the flag will be
set to a one for both sides (unless a semaphore request fromthe other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out
writes fromthe other side is what makes semaphore flags useful in
interprocessor communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location fromthe other
side will be stored in the semaphore request latch for that side until the
semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (
SEM
) and output enable (
OE
)
signals go active. This serves to disallow the semaphore fromchanging
state in the mddle of a read cycle due to a write cycle fromthe other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (
SEM
or
OE
) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no systemlevel contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read fromthat semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, systemcontention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7016S15PFGB | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S15PFGI | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S20GG | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S20GGB | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S20GGI | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7016S15PFGB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S15PFGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S17J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7016S17PF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7016S20G | 功能描述:IC SRAM 144KBIT 20NS 68PGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。