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參數(shù)資料
| 型號： | IDT7025L17JB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | GIGATRUE 550 CAT PATCH CABLE NO BOOT 20FT YELLOW |
| 中文描述： | 高速8K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 294K |
| 代理商： | IDT7025L17JB |
6.16
12
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSY TIMING (M/S = V
IL
)
t
WB
BUSY
Input to Write
(4)
t
WH
Write Hold After
BUSY
(5)
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
t
DDD
Write Data Valid to Read Data Delay
(1)
0
25
—
—
0
25
—
—
0
25
—
—
ns
ns
—
—
60
45
—
—
80
65
—
—
95
80
ns
ns
IDT7025X15
Com'l Only
Min.
IDT7025X17
Com'l Only
Min.
IDT7025X20
IDT7025X25
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3
t
WH
Write Hold After
BUSY
(5)
Parameter
Max.
Max.
Min.
Max.
Min.
Max. Unit
—
—
—
—
5
—
12
15
15
15
15
—
18
—
—
—
—
—
5
—
13
17
17
17
17
—
18
—
—
—
—
—
5
—
15
20
20
20
17
—
30
—
—
—
—
—
5
—
17
20
20
20
17
—
30
—
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
t
WH
Write Hold After
BUSY
(5)
0
—
—
0
13
—
—
0
15
—
—
0
17
—
—
ns
ns
12
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
t
DDD
Write Data Valid to Read Data Delay
(1)
t
WDD
—
—
30
25
—
—
30
25
—
—
45
35
—
—
50
35
ns
ns
IDT7025X35
IDT7025X55
IDT7025X70
Mil. Only
Min.
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3)
t
WH
Write Hold After
BUSY
(5)
Parameter
Min.
Max.
Min.
Max.
Max.
Unit
—
—
—
—
5
—
25
20
20
20
20
—
35
—
—
—
—
—
5
—
25
45
40
40
35
—
40
—
—
—
—
—
5
—
25
45
40
40
35
—
45
—
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
BUSY
(M/
S
= V
IH
)" or "Timing Waveform
of Write With Port-To-Port Delay (M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0ns, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited pn Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. "X" in part numbers indicates power rating (S or L).
2683 tbl 15
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(6)
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