參數(shù)資料
型號: IDT7025L17JB
廠商: Integrated Device Technology, Inc.
英文描述: GIGATRUE 550 CAT PATCH CABLE NO BOOT 20FT YELLOW
中文描述: 高速8K的× 16 DUAL-PORT靜態(tài)RAM
文件頁數(shù): 13/20頁
文件大?。?/td> 294K
代理商: IDT7025L17JB
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.16
13
TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY
(M/
S
= V
IH
)
(2,4,5)
2683 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
t
BAA
TIMING WAVEFORM OF WRITE WITH
BUSY
NOTES:
1. t
WH
must be met for both
BUSY
input (slave) output master.
2. Busy is asserted on port "B" Blocking R/
W
"B"
, until
BUSY
"B"
goes High.
3. t
WB
is only for the 'Slave' Version
.
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(slave).
2.
CE
L
=
CE
R
= V
IL
.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite Port from Port "A".
2683 drw 14
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(2)
(3)
(1)
相關(guān)PDF資料
PDF描述
IDT7025L70F HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
IDT7025L70FB HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
IDT7025L70G HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
IDT7025L70GB HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
IDT7025L70J HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
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