參數(shù)資料
型號: IDT7026L55GB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
中文描述: 16K X 16 DUAL-PORT SRAM, 55 ns, CPGA84
封裝: CERAMIC, PGA-84
文件頁數(shù): 13/18頁
文件大?。?/td> 239K
代理商: IDT7026L55GB
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.17
13
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
BUSY
(M/
S
= V
IH
)
(2,4,5)
2939 drw 12
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
t
BAA
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(slave).
2.
CE
L
=
CE
R
= V
IL.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY (M/
S
= V
IL
)
NOTES:
1. t
WH
must be met for both
BUSY
input (SLAVE) and output (MASTER).
2.
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes High.
2939 drw 13
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(2)
(3)
(1)
相關(guān)PDF資料
PDF描述
IDT7026L55J HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
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