參數(shù)資料
型號: IDT7028L
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM
中文描述: 高速64K的× 16 DUAL-PORT靜態(tài)RAM
文件頁數(shù): 6/17頁
文件大?。?/td> 150K
代理商: IDT7028L
6
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
$88
:;/2
'#
NOTES:
1. Timng depends on which signal is asserted last,
OE
,
CE
,
LB
or
UB
.
2. Timng depends on which signal is de-asserted first
CE
,
OE
,
LB
or
UB
.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
6. Refer to Chip Enable Truth Table.
$/
Input Pulse Levels
Figure 2. Output Test Load
(for t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
Figure 1. AC Output Test Load
4836 drw 04
893
30pF
347
5V
DATA
OUT
BUSY
INT
893
5pF*
347
5V
DATA
OUT
4836 drw 03
t
RC
R/
W
CE
ADDR
t
AA
t
ACE
OE
UB
,
LB
4836 drw 05
(4)
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
(6)
CE
4836 drw 06
t
PU
I
CC
I
SB
t
PD
(6)
50%
50%
.
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
4836 tbl 11
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